This invention relates to output buffers. In particular, this invention provides for improved speeds and reduced layout size and complexity in output buffers.
As shown in FIG. 1, output buffer 1 comprises pull-up transistor 102 and push-down transistor 104. Data input signal DI and output enable signal OE control the turning on and turning off of pull-up transistor 102 and push-down transistor 104. When output enable signal OE and data input signal DI are both high, pull-up transistor 102 is turned on and push-down transistor 104 is turned off. When output enable signal OE is high and data input signal DI is low, pull-up transistor 102 is turned off and push-down transistor 104 is turned on. The disadvantages of this circuit lie in that when pull-up transistor 102 (or push-down transistor 104) is turned on or off, serious current spikes often occur. The current spikes flow through the impedance and inductance component of the power source wires and the ground wire. Therefore, much noise is generated in the internal power source and the ground voltage. Too much noise may cause abnormal operation of the device--especially in the case of multi-output buffers.
To overcome the disadvantages of output buffer 1, another output buffer 2 has been developed as shown in FIG. 2. Pull-up element 202 includes three pull-up transistors 206, 208 and 210, connected in parallel, and push-down element 204 includes push-down transistors 212, 214 and 216, also connected in parallel. The turn-on and turn-off operation of the transistors is sequential, so the current spikes are effectively controlled. In VLSI circuitry, with respect to the output terminals of the general output buffer, the desired drive load ranges from tens of PFs to one hundred PFs. Thus, the width of the pull-up and push-down transistors are relatively large. Particularly with high-speed devices, the transistor width can range from hundreds of microns to one thousand microns. Pull-up transistor 202 and push-down transistor 204 in FIG. 2 include six transistors 206, 208, 210, 212, 214 and 216, each having a transistor width about one third of that of transistor 102 or transistor 104 in FIG. 1. Although this conventional output buffer can reduce the current spikes, the layout pattern is too complicated and the layout area is too large.
In addition, after a period of charge time in the pull-up element, the gate-to-source voltage V.sub.GS and the drain-to-source voltage will be smaller and smaller, resulting in a slower charge speed in the latter half of the charge time. Therefore, although this kind of output buffer circuit design improves the problem of the noise, the speed is still not satisfactory.
As shown in output buffer 3 of FIG. 3, pull-up element 302 includes two pull-up transistors 306 and 308, in parallel, and the push-down element includes two push-down transistors 310 and 312, also in parallel. The gate of pull-up transistor 306 is electrically connected to node 314 for receiving the normal turn-on voltage, and the gate of pull-up transistor 308 is electrically connected to bootstrap 316 for receiving a delayed turn-on voltage. This circuit can improve the problem of noise and fasten the charge speed, but due to the use of two pull-up transistors and two push-down transistors, the problems of a complicated layout and a large layout area still exist.